This invention relates to semiconductor memory devices, and more particularly to a VMOS or vertically oriented channel, silicon gate, read only memory and a process for making it.
Semiconductor memory devices are widely used in the manufacture of digital equipment such as minicomputers and microprocessor systems. Storage of fixed programs is usually provided in these systems by MOS read only memory devices or "ROMs". ROMs are made by semiconductor manufacturers on special order, the programming code being specified by the customer. The manufacturing process is lengthy, requiring dozens of steps, each taking up time and introducing materials handling and inventory factors. Customers require the turn-around time or cycle time between receipt of the ROM code for a custom order and delivery of finished parts to be kept as short as possible. For this reason, programming should be done late in the manufacturing process, but previous ways of doing this required large cell size. The economics of maufacture of ROMs, and of mounting them on circuit boards in the system, are such that the number of memory bits per semiconductor chip is advantageously as high as possible. ROMs of up to 32K bits (32768) are typical at present. Within a few years, standard sizes will progress through 64K, 128K, 256K and 1 megabit. This dictates that the cell size for the storage cells of the ROM be quite small. P-channel ROMs of small size can be relatively easily fabricated in the manner set forth in U.S. Pat. No. 3,541,543, assigned to Texas Instruments, but usually these are programmed by the gate level mask which is at an early stage in the process. Most microprocessor and computer parts are now made by the N-channel silicon gate process because of the shorter access times provided. In the past, the N-channel process has not been favorable to layout of ROM cells of small size and/or programming has been by the moat mask, also early in the process. N-channel ROMs are disclosed in prior applications Ser. No. 762,612, filed Jan. 29, 1977 to become U.S. Pat. No. 4,151,020 Apr. 24, 1979 and Ser. No. 701,932, filed July 1, 1976, assigned to Texas Instruments. Very small cell sizes have been reported for ROMs made by the VMOS process wherein each cell transistor is vertically oriented in a V-groove formed by anisotropic etch. A method of programming a ROM by ion implant prior to forming the ploysilicon gate is shown in U.S. Pat. No. 4,059,826 to Gerald D. Rogers, assigned to Texas Instruments. Also, previous cells have been programmed at the metal level mask by contact areas between metal lines and polysilicon gates, using excessive space on the chip.
In my copenidng application Ser. No. 890,556, filed herewith, I describe a method of programming a ROM array by ion implant through the polysilicon gate and gate oxide; this is done after the metal interconnections in the periphery are patterned, so virtually finished slices can be stored awaiting programming codes.
It is the principal object of this invention to provide a VMOS ROM of small size which may be programmed at a late stage in the manufacturing process. Another object is to provide a small-area MOS ROM cell which is made by a process compatible with standard N-channel silicon gate manufacturing techniques and is programmable after the metal interconnections have been applied and patterned.